Static-current and circuit-level leakage tests are widely used to detect IC defects. However, these methods typically employ customer-defined or system level leakage limit requirements that are frequently too lenient and therefore incapable of removing devices that significantly stray from the desired population "outliers." Historically, these device outliers have been proven to exhibit relatively poor early life performance. This weakness has been somewhat overcome through the use of statistically-based, production-level leakage limits to remove device outliers from production shipments. However, the quality and cost effectiveness of this method is limited by process-dependent, intrinsic transistor leakage variability.
Historically, many improvements in device deliverable quality and reliability have been attained through the use of statistically-based leakage limits (SBLL) as a means of removing leakage outliers from production shipments. These techniques are based on the theory that intrinsically good circuits exhibit a gaussian-like distribution of leakage current measurements. Conversely, devices containing point defects exhibit abnormally high leakage values relative to the parent population.
SBLL techniques employ descriptive statistics from a normal distribution of leakage current measurements to calculate .+-.3 sigma test limits that encompass 99.7% of the parent population. Devices that fall outside the SBLL include those that have been degraded by point defects. Aging experiments have consistently shown that this subset of leakage outliers yields significantly higher early life failure rates than the parent population. As a result, circuit designs tested using SBLL methods typically have higher levels of quality and reliability than products screened against customer-defined or system level requirement leakage limits.
Although SBLL techniques can significantly improve quality, the most significant detractor to their widespread use is the potential for high manufacturing costs resulting from excessive yield loss. This problem is most evident when the wafer fabrication process drifts near its allowable operating extremes causing the intrinsic semiconductor and circuit-level leakage characteristics to shift significantly. When this occurs, manufacturing yields become suppressed by a magnitude that is proportional to the shift in the leakage distribution. This yield suppression occurs because the previously defined SBLL become invalid, since the mean and sigma values from which they were derived no longer apply. Issues centered on the cost, quantity, and shipping requirements of said product typically result in burn-in evaluation experiments of the marginal leakage failures. These evaluations typically support the release of affected product to meet immediate customer demand, thereby reducing organizational support of SBLL test methods and ultimately resulting in poorer outgoing quality.
Another less apparent weakness of conventional SBLL methods stems from normal time-based process variations. These variations are reflected in circuit level leakage measurements even though their impact may seem relatively superficial. However, during a process capability study phase in which a cross-section sampling of production lots are evaluated, even minor time-based process variations can act to distort the calculated standard deviation of circuit level leakage from which SBLLs are derived. Excessively wide SBLL may result, which reduce defect-screening effectiveness by allowing some leakage outliers near the tails of the parent population to be shipped to the customer.
Accordingly, what is needed in the art is an effective method of screening leakage outliers from the intrinsic parent population with minimal negative impact on manufacturing costs and customer service.